This invention relates to digital transversal filters of the type having a delay line including multiple stages which are clocked by timing signals to shift an input signal through the delay line, weighting means for weighting outputs of each of the stages of the delay line, and summing means for summing the weighted outputs of the stages of the delay line to synthesize a summed output.
Transversal filters of the general type described above are disclosed for example in Somer U.S. Pat. No. 4,773,082, assigned to the assignee of the present invention. The transversal filter of the Somer patent includes two delay lines made up of flip flops which function collectively as a shift register. As pointed out in the Somer patent, it is advantageous for many applications to have such a shift register shift multiple times per data bit. However, when the data bit is produced at a high rate, it may not be practical or economically feasible to operate the shift register at a large multiple of the frequency of the incoming data. The Somer patent addresses this problem with a shift register that is clocked at the same rate as the data, yet which shifts several times per data bit. In the particular example given in the Somer patent, the shift register shifts four times per data bit by using four clocks, each having the same frequency as the data bits, but each phase shifted by a phase angle of 90.degree. with respect to the next adjacent clock.
It is an object of the present invention to provide a digital transversal filter which shifts multiple times per data bit, yet which requires a smaller number of separately phased clock signals for the shift register.